Publications: Conferences, Journals, and Patents

Efficient SoC architectures for autonomous aerial robots:
1) The Sky is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines
     Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Paul Whatmough, Aleksandra Faust, Gu-Yeon Wei, David Brooks, and Vijay Reddi
     Accepted to appear in IEEE Computer Architecture Letters (CAL 2020) [pdf]
Heterogeneous accelerator-based system-on-chip (SoC) architectures: 
Detailed simulation framework for deep neural network (DNN) accelerator-based SoCs:
2) SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads
     Sam (Likun) Xi, Yuan Yao, Kshitij Bhardwaj, Paul Whatmough, Gu-Yeon Wei, and David Brooks 
     To be submitted to ACM Transactions on Architecture and Code Optimization (TACO), available on Arxiv [pdf]
Finding the best coherence models for accelerators of complex SoCs using machine learning:
4) Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization
     Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, Jose Miguel Hernandez Lobato, and Gu-Yeon Wei
     In IEEE Computer Architecture Letters (CAL 2019), pp. 119-123 [pdf]
Machine learning-based design space exploration framework for heterogeneous SoCs:
5) A Bayesian Optimization-Based Efficient Design Space Exploration Framework for Many-Accelerator SoCs
     Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, Jose Miguel Hernandez Lobato, and Gu-Yeon Wei
     In SRC Techcon Workshop, 2019
Asynchronous ('clockless') Networks-on-chip (NoCs): 
Methodology to synthesize asynchronous NoCs on commercial FPGAs:
6) Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs
      Kshitij Bhardwaj, Paolo Mantovani, Luca Carloni, and Steven M. Nowick
      Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2019), Lausanne, Switzerland, pp. 1-6 [pdf]
Supporting efficient multicast (1-to-many communication) in asynchronous NoCs:
8) Global and Local Time-Step Determination Schemes For Neural Networks
     Gregory K. Chen, Kshitij Bhardwaj, Raghavan Kumar, Huseyin E. Sumbul, Phil Knag, Ram K. Krishnamurthy, Himanshu Kaul
     US Patent Application: 2019/0102669, Patent Application Publication Date: April 4, 2019 [pdf]
7) A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs
     Kshitij Bhardwaj and Steven M. Nowick
     In IEEE Transactions on Very Large Scale Integration Systems (TVLSI 2019), pp. 350-363 [pdf]
9) Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer
     Kshitij Bhardwaj, Weiwei Jiang and Steven M. Nowick
     Proceedings of International Symposium on Networks-on-Chip (NOCS 2017), Seoul, South Korea, pp. 1-8
     (Best paper nomination) [pdf]
10) Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
     Kshitij Bhardwaj and Steven M. Nowick
     Proceedings of Design Automation Conference (DAC 2016), Austin, TX, pp. 38:1-38:6 [pdf]
Optimizing performance of unicast traffic in asynchronous NoCs: 
11) A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's
     Weiwei Jiang, Kshitij Bhardwaj, Geoffray Lacourba and Steven M. Nowick
     Proceedings of Design Automation Conference (DAC 2015), San Francisco, CA, pp. 203:1-203:6 [pdf]
Mitigating impact of aging and process variation on NoCs:
12) Aging-Aware Routing for NoCs
     Kshitij Bhardwaj, Koushik Chakraborty and Sanghamitra Roy
     US Patent: 9344358, Date of Patent: May 17, 2016 [pdf]
13) Wearout Resilience in NoCs Through An Aging Aware Routing Algorithm
       Dean Ancajas, Kshitij Bhardwaj, Koushik Chakraborty and Sanghamitra Roy
       IEEE Transactions on Very Large Scale Integration Systems (TVLSI 2015), vol.23, no.2, pp. 382-391 [pdf]
14) Towards Graceful Aging Degradation in NoCs Through Adaptive Routing Algorithm
       Kshitij Bhardwaj, Koushik Chakraborty and Sanghamitra Roy
       Proceedings of Design Automation Conference (DAC 2012), San Francisco, CA, pp. 382-391 [pdf]
15) An MILP-Based Aging Aware Routing Algorithm for NoCs
       Kshitij Bhardwaj, Koushik Chakraborty and Sanghamitra Roy
       Proceedings of Design, Automation & Test in Europe (DATE 2012), Dresden, Germany, pp. 326-341 [pdf]
Task scheduling algorithms to optimize power and performance of SoCs and NoCs:
16) Power-Performance Yield Optimization for MPSoCs Using MILP
       Kshitij Bhardwaj, Sanghamitra Roy and Koushik Chakraborty
       Proceedings of International Symposium on Quality Electronic Design (ISQED 2012), Santa Clara, CA, pp. 764-771 [pdf]
17) Energy and Bandwidth Aware Mapping of IPs onto Regular NoC Architectures Using Multi-Objective Genetic
      Algorithms
       Kshitij Bhardwaj and Rabindra K. Jena
       Proceedings of International Symposium on System-on-Chip (ISSoC 2009), Tampere, Finland, pp. 27-31 [pdf]
 
18) 1.5V High Performance Op-Amp Using Self Cascode Structure
        Kshitij Bhardwaj and S.S. Rajput
        Proceedings of IEEE Student Conference on Research and Development (SCOReD 2009), UPM Serdang, pp. 254- 257 [pdf]
High-performance op-amp design:
3) A Comprehensive Methodology to Determine Optimal Coherence interfaces for Many-Accelerator SoCs
     Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, Jose Miguel Hernandez Lobato, and Gu-Yeon Wei
     Accepted to appear in International Symposium on Low Power Electronics and Design (ISLPED 2020), Boston, MA

© 2016 by Kshitij Bhardwaj. Proudly created with Wix.com

  • Facebook - Grey Circle
  • Twitter - Grey Circle
  • Google+ - Grey Circle
  • LinkedIn - Grey Circle